Leakage power measurement and characterization of Integrated Circuits (IC) may be important in many design, run time management, and testing tasks. Manufacturing variability and operational and environmental conditions in post-silicon IC's may render leakage power characteristics of various devices, such as transistors, gates and so forth, unpredictable and/or unknown. Component feature sizes, for example, CMOS (Complementary Metal Oxide Semiconductor) features, are often aggressively scaled down to meet the growing demand for lowering the cost-per-function by increasing the device density and computational speed. Because of the random inaccuracy in manufacturing at small scales, variations in device feature sizes tend to be pretty common. As a result, Very Large Scale Integrated (VLSI) circuits may show highly variable power characteristics. The power consumption of an IC may not a deterministic function of the design at VLSI scales, where each chip may exhibit a specific profile for both static and dynamic power consumptions.
Technology scaling has also generally caused power behavior to become a substantive design objective for many classes of ICs and for systems that include the ICs. Initially, power switching was typically the dominant power consideration in the IC design process. However, technology scaling may have had an impact on the static (leakage) power consumption of circuits. Due to unabated silicon feature scaling, elevated leakage current has tend to become an increasingly dominant power consideration in the recent and future designs of ICs. Indeed, there are predictions that leakage current may surpass power switching as the dominant design consideration in upcoming generations of scaled circuit designs.